An integrated circuit (IC) is formed by creating one or more devices (e.g., circuit components) on a semiconductor substrate using a fabrication process. As fabrication processes and materials improve, semiconductor device geometries continue to decrease in size since such devices were first introduced several decades ago. For example, current fabrication processes are producing devices having feature geometry sizes (e.g., the smallest component (or line) that may be created using the process) of less than 90 nm. However, the reduction in size of device geometries frequently introduces new challenges that need to be overcome.
As microelectronic device geometries are scaled below 65 nm, the electrical efficiency becomes an issue that impacts device performance. Microelectronic device performance such as current gain can be significantly affected by the configuration and materials comprising and incorporated into microelectronic devices. To enhance the electrical efficiency, a strained silicon-germanium layer has been proposed to provide a compressive stress to a channel of a transistor for providing a desired electronic mobility.